The CS undergraduate programme at NUAA includes a (compulsory) Computer Organization course for this (4th) semester that requires implementing a MIPS CPU on the Loongson development kit, which is essentially a FPGA board + various useful modules.

As shown below, the suggested design is a classical 5-stage pipelined architecture:

Suggested basic 5-stage pipeline

But it's boring to write "yet another" CPU that implements only the simplest structures. So I decided to extend the design a bit, and build a superscalar OoO architecture from the ground up.

During the next few months I will post my experience as a series of posts both here and on WeChat. Subscribe to stay updated!